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GALVANTECH, INC.
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
SYNCHRONOUS 256K x 18 SRAM ZBL SRAM +3.3V SUPPLY, 2-BIT BURST COUNTER FLOW-THRU OUTPUT SELECTABLE BURST MODE
FEATURES
* * * * * * * * * * * * * * Zero Bus Latency, no dead cycles between write and read cycles Fast clock speed: 100, 83, 67, and 50MHz Fast access time: 9, 10, 11, 15ns Internally synchronized registered outputs eliminate the need to control OE# Single 3.3V -5% and +5% power supply Single R/W# (READ/WRITE) control pin Positive clock-edge triggered, address, data, and control signal registers Interleaved or linear 4-word burst capability Individual byte write (BWa# - BWb#) control (may be tied LOW) CKE# pin to enable clock and suspend operations Three chip enables for simple depth expansion SNOOZE MODE for low power standby Automatic power down Packaged in a JEDEC standard 100-pin TQFP package All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (CE#, CE2# and CE2), cycle start input (ADV/LD#), clock enable (CKE#), byte write enables (BWa# and BWb#), and read-write control (R/W#). Address and control signals are applied to the SRAM during one clock cycle, and one cycle later, its associated data occurs, either read or write. A clock enable (CKE#) pin allows operation of the GVT71256ZB18 to be suspended as long as necessary. All synchronous inputs are ignored when (CKE#) is high and the internal device registers will hold their previous values. There are three chip enable pins (CE#, CE2, CE2#) that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD# is low, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high impedance state one cycle after chip is deselected or a write cycle is initiated. The GVT71256ZB18 has an on-chip 2-bit burst counter. In the burst mode, the GVT71256ZB18 provides four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD# signal is used to load a new external address (ADV/LD#=LOW) or increment the internal burst counter (ADV/LD#=HIGH) Output enable (OE#), snooze enable (ZZ) and burst sequence select (MODE) are the asynchronous signals. OE# can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used. The GVT71256ZB18 utilizes high performance high volume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
OPTIONS
* Timing 9.0ns access/10.0ns cycle 10.0ns access/12.0ns cycle 11.0ns access/15.0ns cycle 15.0ns access/20.0 cycle Packages 100-pin TQFP
MARKING
-9 -10 -11 -15
*
T
GENERAL DESCRIPTION
The GVT71256ZB18 SRAM is designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. This SRAM is optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). It integrates 262,144x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. The Galvantech Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site www.galvantech.com
Rev. 7/98
Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
ZZ MODE
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
Address
ADV/LD# R/W# BWa#, BWb# 256K x 9 x 2 SRAM Array CKE#
Control
SA0, SA1, SA
Control Logic
Mux
CLK
OE#
Output Buffers
DQa-DQb, DQPa, DQPb
NOTE:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
July 23, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
DO Sel
DI
CE#, CE2#, CE2
Input Registers
GALVANTECH, INC.
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
PIN ASSIGNMENT (Top View)
SA SA CE# CE2 NC NC BWb# BWa# CE2# VCC VSS CLK R/W# CKE# OE# ADV/LD# NC NC SA SA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb VSS VCC VCC VSS DQb DQb VCCQ VSS DQb DQb DQPb NC VSS VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA NC NC VCCQ VSS NC DQPa DQa DQa VSS VCCQ DQa DQa VSS VSS VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PIN DESCRIPTIONS
TQFP PINS
37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 99, 100 93, 94
SYMBOL
SA0, SA1, SA
TYPE
InputSynchronous
BWa#, BWb#,
InputSynchronous
87
CKE#
InputSynchronous
88
R/W#
InputSynchronous
89
CLK
InputSynchronous
MODE SA SA SA SA SA1 SA0 NC NC VSS VCC NC NC SA SA SA SA SA SA SA
DESCRIPTION
Synchronous Address Inputs: The address register is triggered by a combination of the rising edge of CLK, ADV/LD# LOW, CKE# LOW and true chip enables. SA0 and SA1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated.
Synchronous Byte Write Enables: Each 9-bit byte has its own active low byte write enable. On load write cycles (when R/W# and ADV/LD# are sampled LOW), the appropriate byte write signal (BWx#) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte write signals are ignored when R/W# is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BWa# controls DQa and DQPa pins; BWb# controls DQb and DQPb pins. BWx# can all be tied LOW if always doing write to the entire 18-bit word. Synchronous Clock Enable Input: When CKE# is sampled HIGH, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CKE# sampled HIGH on the device outputs is as if the low to high clock transition did not occur. For normal operation, CKE# must be sampled LOW at rising edge of clock. Read Write: R/W# signal is a synchronous input that identifies whether the current loaded cycle and the subsequent burst cycles initiated by ADV/LD# is a Read or Write operation. The data bus activity for the current cycle takes place one clock cycle later. Clock: This is the clock input to GVT71256ZB18. Except for OE#, ZZ and MODE, all timing references for the device are made with respect to the rising edge of CLK.
July 23, 1998
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Rev. 7/98
GALVANTECH, INC.
PIN DESCRIPTIONS (continued)
TQFP PINS
98, 92
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
SYMBOL
CE#, CE2#
TYPE
Input-
DESCRIPTION
Synchronous Active Low Chip Enable: CE# and CE2# are used with CE2 to enable the Synchronous GVT71256ZB18. CE# or CE2# sampled HIGH or CE2 sampled LOW, along with ADV/ LD# LOW at the rising edge of clock, initiates a deselect cycle. The data bus will be HIGH-Z one clock cycle after chip deselect is initiated. inputSynchronous
97 86
CE2 OE#
Synchronous Active High Chip enable: CE2 is used with CE# and CE2# to enable the chip. CE2 has inverted polarity but otherwise is identical to CE# and CE2#. Asynchronous Output Enable: OE# must be LOW to read data. When OE# is HIGH, the I/O pins are in high impedance state. OE# does not need to be actively controlled for read and write cycles. In normal operation, OE# can be tied LOW. Advance/Load: ADV/LD# is a synchronous input that is used to load the internal registers with new address and control signals when it is sampled LOW at the rising edge of clock with the chip is selected. When ADV/LD# is sampled HIGH, then the internal burst counter is advanced for any burst that was in progress. The external addresses and R/W# are ignored when ADV/LD# is sampled HIGH. Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence is selected. When MODE is LOW, the linear burst sequence is selected. MODE is a static DC input. Snooze Enable: This active HIGH input puts the device in low power consumption Data Inputs/Outputs: Both the data input path and data output path are registered and triggered by the rising edge of CLK. Byte "a" is DQa pins; Byte "b" is DQb pins.
Input
85
ADV/LD#
InputSynchronous
31 64 58, 59, 62, 63 68, 69, 72, 73, 8, 9, 12, 13 18, 19, 22, 23 74, 24
MODE ZZ DQa DQb
InputStatic InputInput/ Output
Asynchronous standby mode. For normal operation, this input has to be either LOW or NC.
DQPa, DQPb
Input/ Output Supply Ground I/O Supply -
Parity Inputs/Outputs: Both the data input path and data output path are registered and triggered by the rising edge of CLK. DQPa is parity bit for Byte "a"; DQPb is parity bit for Byte "b". Power Supply: +3.3V -5% and +5%. Ground: GND. Output Buffer Supply: +3.3V -5% and +5%. No Connect: These signals are not internally connected.
15, 16, 41, 65, 91 5, 10, 14, 17, 21, 26, 40, 55, 60, 66, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 1-3, 6, 7, 25, 28-30, 38, 39, 42, 43, 51-53, 56, 57, 75, 78, 79, 83, 84, 95, 96
VCC VSS VCCQ NC
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or NC)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A00 A...A11 A...A10
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)1
A...A11 A...A10 A...A01 A...A00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A10 A...A11 A...A00
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)1
A...A11 A...A00 A...A01 A...A10
Note: 1. Upon completion of the Burst sequence, the counter wraps around to its initial state and continues counting.
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Rev. 7/98
GALVANTECH, INC.
PARTIAL TRUTH TABLE FOR READ/WRITE1
FUNCTION R/W#
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
BWa#
BWb# X H H L L
Read H X No Write L H Write Byte a (DQa, DQPa)2 L L 2 Write Byte b (DQb, DQPb) L H Write all bytes L L Note:1 1. L means logic LOW. H means logic HIGH. X means "Don't Care."
2.
Multiple bytes may be selected during the same cycle.
FUNCTIONAL TIMING DIAGRAM
CYCLE CLOCK ADDRESS (SA0, SA1, SA) n+19 n+20 n+21 n+22 n+23 n+24 n+25 n+26 n+27
A19
A20
A21
A22
A23
A24
A25
A26
A27
CONTROL (R/W#, BWx#, ADV/LD#)
C19
C20
C21
C22
C23
C24
C25
C26
C27
DATA DQ[a:b] DQP[a:b]
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
Note: 1. This assumes that CKE#, CE#, CE2 and CE2# are all True. 2. All addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. Data out is valid after a clock-to-data delay from the rising edge of clock.
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TRUTH TABLE(1-9)
OPERATION
DESELECT CYCLE CONTINUE DESELECT/NOP READ CYCLE (BEGIN BURST) READ CYCLE (CONTINUE BURST) DUMMY READ (BEGIN BURST) DUMMY READ (CONTINUE BURST) WRITE CYCLE (BEGIN BURST) WRITE CYCLE (CONTINUE BURST) ABORT WRITE (BEGIN BURST) ABORT WRITE (CONTINUE BURST) IGNORE CLOCK EDGE /NOP
PREVIOUS CYCLE
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
ADDRESS USED X X External Next External Next External Next External Next X
R/W#
ADV/LD#
CE#
CKE#
BWx#
OE#
DQ (1 cycle later)
NOTES
X
DESELECT
X X H X H X L X L X X
L H L H L H L H L H H
H X L X L X L X L X X
L L L L L L L L L L H
X X X X X X L L H H X
X X X X H H X X X X X
High-Z High-Z Q Q High-Z High-Z D D High-Z High-Z 10 11 10, 11 12 10 11 10, 11 10
X READ X READ X WRITE X WRITE X
Note: 1. L means logic LOW. H means logic HIGH. X means "Don't Care." High-Z means HIGH IMPEDANCE. BWx# = L means 2. 3. 4. 5. 6. 7. 8. 9.
[BWa#*BWb#] equals LOW. BWx# = H means [BWa#*BWb#] equals HIGH. CE# equals H means CE# and CE2# are LOW along with CE2 being HIGH. CE# equals L means CE# or CE2# is HIGH or CE2 is LOW. CE# equals X means CE#, CE2# and CE2 are "Don't Care."
BWa# enables WRITE to byte "a" (DQa and DQPa pins). BWb# enables WRITE to byte "b" (DQb and DQPb pins). The device is not in SNOOZE MODE, i.e. the ZZ pin is LOW. During SNOOZE MODE, the ZZ pin is HIGH and all the address pins and control pins are "Don't Care." The SNOOZE MODE
can only be entered 1 cycle after the WRITE cycle, otherwise the WRITE cycle may not be completed.
All inputs, except OE#, ZZ and MODE pins, must meet setup time and hold time specification against the clock (CLK) LOW-to-HIGH transition edge. OE# may be tied to LOW for all the operation. This device automatically turns off the output driver during WRITE cycle.
Device outputs are ensured to be in High-Z during device power-up.
This device contains a 2-bit burst counter. The address counter is incremented for all CONTINUE BURST cycles. Address wraps to the initial address every fourth burst cycle. 10. CONTINUE BURST cycles, whether READ or WRITE, use the same control signals. The type of cycle performed, READ or WRITE, depends upon the R/W# control signal at the BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle is executed first. 11. DUMMY READ and ABORT WRITE cycles can be entered to setup subsequent READ or WRITE cycles or to increment the burst counter. 12. When an IGNORE CLOCK EDGE cycle enters, the output data (Q) will remain the same if the previous cycle is READ cycle or remain High-Z if the previous cycle is WRITE or DESELECT cycle.
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Rev. 7/98
GALVANTECH, INC.
ABSOLUTE MAXIMUM RATINGS*
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN ...........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +125o Junction Temperature .....................................................+125o Power Dissipation ............................................................2.0W Short Circuit Output Current ..........................................50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0oC Ta
70C; VCC = 3.3V -5% and +5% unless otherwise noted)
CONDITIONS
Data Inputs (DQxx) All Other Inputs
DESCRIPTION
Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current
SYMBOL
VIHD VIH VIl ILI ILI ILO VOH VOL VCC VCCQ
MIN
2.0 2.0 -0.5 2.4
MAX
VCC+0.3 4.6 0.8 5 30 5 0.4
UNITS
V V V uA uA uA V V V V
NOTES
1,2 1,2 1, 2 6
0V < VIN < VCC
MODE and ZZ Input Leakage 0V < VIN < VCC Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage I/O Supply Voltage Output(s) disabled, 0V < VOUT < VCC IOH = -5.0mA IOL = 8.0mA
1 1 1 1
3.135 3.135
3.465 VCC
DESCRIPTION
Power Supply Current: Operating CMOS Standby
CONDITIONS
Device selected; all inputs < VILor > VIH;cycle time > tKC MIN; VCC =MAX; outputs open, ADV/LD# = X, f = fMAX2 Device deselected; VCC = MAX; all inputs < VSS +0.2 or >VCC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH ; all inputs static; VCC = MAX; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = MAX; CLK cycle time > tKC MIN
SYM
Icc
TYP
150
-9
300
-10
260
-11
220
-15
170
UNITS NOTES
mA 3, 4, 5, 7
ISB2
5
10
10
10
10
mA
4, 5, 7
TTL Standby
ISB3
20
40
40
40
40
mA
4, 5, 7
Clock Running
ISB4
40
70
65
55
45
mA
4, 5, 7
Note:
1. 2. 3. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +6.0V for t tKC /2 VIL -2.0V for t tKC /2.
Icc is given with no output current. Icc increases with greater output loading and faster cycle times.
4. "Device Deselected" means the device is in POWER -DOWN mode as defined in the truth table. "Device Selected" means the device is active. 5. Typical values are measured at 3.3V, 25oC and 20ns cycle time. 6. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of +30 A. 7. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f = 0 means no input lines are changing.
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AC ELECTRICAL CHARACTERISTICS
(Note 2) (0oC
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
TA 70oC; VCC = 3.3V -5% and +5%)
-9 100MHz
SYM MIN MAX
DESCRIPTION
Clock Clock cycle time Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup Times Address and Controls Data In Hold Times Address and Controls Data In
t t t t t t t t t t
- 10 83MHz
MIN MAX
-11 67MHz
MIN MAX
- 15 50MHz
MIN MAX UNITS NOTES
KC KH KL
10.0 3.0 3.0 9.0 3.0 4.0 5.0 5.0 0 5.0 2.0 2.0 0.5 0.5
12.0 3.0 3.0 10.0 3.0 4.0 5.0 5.0 0 5.0 2.0 2.0 0.5 0.5
15.0 4.0 4.0 11.0 3.0 4.0 5.0 5.0 0 5.0 2.5 2.5 0.5 0.5
20.0 4.0 4.0 15.0 3.0 4.0 5.0 5.0 0 5.0 2.5 2.5 0.5 0.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 3, 4 1, 3, 4 5 5 5 5 1, 3, 4 1, 3, 4
t
t
KQ
KQX
KQLZ OEQ
KQHZ
t
t
OELZ
OEHZ S
SD H
HD
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 3.3V
SYMBOL
CI CO
TYP
4 7
MAX
4 6.5
UNITS
pF pF
NOTES
1 1
THERMAL CONSIDERATION
DESCRIPTION
Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case
CONDITIONS
Still air, soldered on 4.25 x 1.125 inch 4-layer PCB
SYMBOL
JA JC
TQFP TYP
25 9
UNITS
o o
NOTES
C/W C/W
Note:
1. 2. 3. 4. 5. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined in the truth table.
6. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1.
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AC TEST CONDITIONS Input pulse levels Input slew rate Input timing reference levels Output reference levels Output load 0V to 3V 1.0V/ns 1.5V 1.5V See Figures 1 and 2
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
OUTPUT LOADS
DQ Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
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GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
READ TIMING
tKC t tKL
KH
CLK
t
S
tH
CKE#
t
S
t
H
R/W#
t
S
tH
ADDRESS
A1
A2
BWa#, BWb#
t
S
CE# (See Note)
t
tH
S
t
H
ADV/LD#
OE#
tKQLZ tKQ
Q(A2)
tKQX
Q(A2+1) Q(A2+2)
(CKE# HIGH , eliminates current L-H clock edge) Q(A2+3)
(Burst Wraps around to initial state) Q(A2)
tKQHZ
DQ
Q(A1)
Read
Read
BURST READ
Deselect
Note: 1. Q(A1) represents the first output from the external address A1. Q(A2) represents the first output from the external address A2; Q(A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the state of the MODE input. 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD# LOW. 4. R/W# is "Don't Care" when the SRAM is bursting (ADV/LD# sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM.
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GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
WRITE TIMING
t
KC
t t
KH
KL
CLK
t
S
tH
CKE#
t
S
tH
R/W#
t
S
tH
ADDRESS
A1
t
A2
S BW(A2)
t t
H BW(A2+1) BW(A2+2) BW(A2+3) BW(A2)
BWa#, BWb# CE# (See Note)
BW(A1)
S
t
H
t
S
t
H
ADV/LD#
OE#
tSD tHD
D(A1) D(A2) D(A2+1) D(A2+2) (CKE# HIGH, eliminates current L-H clock edge) (Burst Wraps around to initial state) D(A2+3) D(A2)
DQ
Write
Write
Burst Write
Deselect
Note: 1. D(A1) represents the first input to the external address A1. D(A2) represents the first input to the external address A2; D(A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the state of the MODE input. 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD# LOW. 4. R/W# is "Don't Care" when the SRAM is bursting (ADV/LD# sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
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Rev. 7/98
GALVANTECH, INC.
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
READ/WRITE TIMING
tKC tKH tKL
CLK
tS tH
CKE#
t
S
tH
R/W#
tS tH
ADDRESS
A1
t
A2
S BW(A2)
tS tH
A3
A4
BW(A4)
A5
BW(A5)
A6
A7
A8
A9
BWa#, BWb# CE# (See Note)
t
tH
S
tH
ADV/LD#
OE#
tKQ tKQHZ Q(A1) Read tKQLZ Q(A3) Read D(A2) Write D(A4) Write D(A5) Write tKQX Q(A6) Read D(A8) Q(A7)
DATA Out (Q)
DATA In (D)
Note:
1. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2. 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH. 3. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. .
July 23, 1998
12
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
CKE# TIMING
t
KC
tKL
tKH
CLK
tS t
H
CKE#
tS t
H
R/W#
tS tH
ADDRESS
A1
tS
A2
tH
A3
A4
A5
BWa#, BWb#
tS
CE# (See Note)
t
tH
S
tH
ADV/LD#
OE#
tKQ tKQHZ
DATA Out (Q)
tKQLZ
Q(A 1)
tKQX tSD tHD
Q(A 3)
Q(A 4)
DATA In (D)
D(A2)
Note:
1. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2. 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH. 3. CKE# when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal register in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
July 23, 1998
13
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
CE# TIMING
t
KC
tKH t
KL
CLK
tS tH
CKE#
t
S
tH
R/W#
t
S
tH
ADDRESS
A1
A2
t
A3
S
tH
A4
A5
BWa#, BWb#
t
S
CE# (See Note) ADV/LD#
tOEQ
tH
t
S
tH
OE#
tOELZ tKQHZ tOEHZ
DATA Out (Q)
Q(A1)
tKQLZ tKQ
Q(A2)
tKQX tSD tHD
Q(A4)
DATA In (D)
D(A3)
Note:
1. Q(A1) represents the first output from the external address A1. D(A3) represents the input data to the SRAM corresponding to address A3, etc. 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH. 3. When either one of the Chip enables (CE#, CE2 or CE2#) is sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z one cycle after the initiation of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed. 4. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
July 23, 1998
14
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
100 Pin TQFP Package Dimensions
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
16.00 + 0.10 14.00 + 0.10
#1
20.00 + 0.10
22.00 + 0.10
1.40 + 0.05
1.60 Max Note: All dimensions in Millimeters
0.65 Basic
0.30 + 0.08
0.60 + 0.15
July 23, 1998
15
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
Ordering Information
GVT71256ZB18 256K X 18 FLOW-THROUGH ZBL SRAM
GVT 71256ZB18 X - X
Galvantech Prefix Part Number Speed (9 = 9.0ns access/10ns cycle 10 = 10.0ns access/12ns cycle 11 = 11.0ns access/15ns cycle 15 = 15.0ns access/20ns cycle) Package (T = 100 PIN TQFP)
July 23, 1998
16
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98

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